1. Field of the Invention
The present invention relates to a demodulation circuit for demodulating an FSK signal which comprises a long bit pulse and a short bit pulse.
2. Description of the Related Art
An example of an FSK signal is described with reference to FIG. 5. As shown in FIG. 5, an FSK signal comprises a long bit, which has a long bit period, and a short bit, which has a short bit period. Note that a bit period is a combination of a period with a bit pulse and a period without a bit pulse. Each bit contains a single pulse having a certain length.
In the example of FIG. 1, a long bit contains a pulse having a long length, while a short bit contains a pulse having a short length. Either one of the long or short bits is set to a binary code “1”, while the other is set to a binary code “0”.
As described in Japanese Patent Laid-open Publication No. Hei 9-294143, for example, typical structures of a conventional FSK signal demodulation circuit may include one in which frequency variation is set correlated with voltage variation using a frequency discriminator so that bit determination, namely, determination as to whether 1 or 0, is made based on voltage variation, and another in which a duty ratio of each bit is determined using a clock signal in synchronism with an FSK signal in order to perform bit determination.
Although these demodulation circuits can exhibit preferable demodulation performance, they have a problem of a complicated circuit structure that is large in size.